1. Field of the Invention
The present invention relates generally to bias circuits, and more particularly, to such a bias circuit for establishing bias voltages suitable for biasing current sources.
2. Related Art
FIG. 7A is a circuit diagram of a known, simple current mirror including an input diode M31 and a current source Field Effect Transistor (FET) M32. The simple current mirror simply replicates (perhaps proportionately) the input diode current IIN2 as an output current IOUT2. While this circuit is simple, a problem can arise because the drain-source voltage of FET M31 is not necessarily equal to the drain-source voltage of FET M32. This causes the current IOUT2 flowing through FET M32 to be different from the current IIN2 flowing through diode M31. This is especially the case for devices having relatively short channels (also referred to as short-channel devices), such as sub-micron devices.
FIG. 7B is a circuit diagram of a known cascode current mirror used to solve the above-mentioned problem. The cascode current mirror keeps the drain-source voltages of both FETs M33 and M34 the same. However, the voltage at the top of FET M35 (that is, on the drain of FET M35) can be relatively high, perhaps more than ½ the power supply voltage VDD. Therefore, changes in voltage VDD cause significantly larger corresponding changes in input current. All of this amounts to a circuit having the disadvantage of very high power supply sensitivity (that is, an undesired sensitivity to power supply voltage variations).
FIG. 7C is a circuit diagram of a self-biased current mirror used to overcome the above-mentioned power supply sensitivity. The current through M42 is basically the voltage across diode M41 divided by the resistance of R10. This current can then be mirrored to the output through the p-type Metal Oxide Semiconductor (PMOS) devices M44-M46. Such self-biased reference circuits also need a start-up circuit to ensure they attain a proper operating state. The circuit of FIG. 7C tends to have the disadvantage that currents in the circuit tend to vary in undesired or wrong directions over process and temperature variations. Also, the input current can not be conveniently adjusted.
FIG. 7D is a bandgap circuit using parasitic bipolar transistors in a Complementary Metal Oxide Semiconductor (CMOS) substrate to create controlled reference voltages. One voltage goes as delta-VBE and the other goes as KT/q multiplied up. Since the temperature coefficients of each of these voltages go in opposite directions, a temperature independent voltage can be achieved. However, bandgap references tend to require a start-up circuit to ensure proper operation thereof. Also, the bandgap circuit is not space-efficient because of the large area required by the PNP transistors used in the circuit. PNP transistors are lateral (not vertical) devices with poor beta and very low maximum current.
There is a need therefore for an improved bias circuit that overcomes all of the above-mentioned shortcomings and disadvantages of known circuits.